The present invention relates to a circuit which is assembled in each of various sensors for sensing a physical quantity as an electric signal and processes the output signal and, more particularly, to a sensor adjusting circuit suitable for use in a capacitive acceleration sensor or a hot-wire air flow sensor.
In a sensor such as a capacitive acceleration sensor for sensing a physical quantity as an electric signal, it is necessary to adjust so that the scale of the physical quantity to be sensed and the scale of the output signal have a desired relation.
A process necessary for satisfying the desired relation is called scale adjustment (calibration) and a circuit assembled in a sensor for the process is a sensor adjusting circuit. Plainly speaking, the sensor adjusting circuit is nothing but a converting circuit for giving predetermined input/output characteristics.
The contents of the process carried out by the sensor adjusting circuit are generally span adjustment and offset adjustment. In this case, the span adjustment corresponds to sensitivity adjustment, and the offset adjustment corresponds to zero point adjustment.
A sensor adjusting circuit which uses a memory in which data necessary to be outputted is stored in a predetermined address and makes the address of the memory correspond to the level of an input signal, thereby outputting data to be read out as an output signal is conventional employed.
For example, Japanese Patent Application Laid-Open No. 3-51714 discloses a PROM (programmable read only memory) of a Zener zapping system and a method of selecting a leading part of a resistor array in accordance with the contents of data of the PROM, thereby adjusting a sensor output. There is disclosed another method of adjusting an sensor output by changing a circuit constant of a switched capacitor circuit on the basis of information written in the PROM.
On the other hand, for example, in Japanese Patent Application Laid-Open No. 8-62010, a method of adjusting a sensor output by using an A/D converter (analog-to-digital converter) and a CPU (central processing unit) is proposed.
As will be described hereinbelow, some of the conventional techniques do not consider limitation of expansion of the adjustment range and improvement in the accuracy. The other conventional technique does not consider that suppression of increase in the circuit scale is limited and has a problem with improvement of the cost performance.
With respect to the conventional techniques such as the method of selecting the leading part of the resistor array and the method of changing the circuit constant of the switched capacitor circuit, the circuit structure is easily formed on a chip. When expansion of the adjustment range and increase in accuracy are attempted, however, exponential increase in the circuit scale is accompanied so that the expansion of the adjustment range and the increase in accuracy are limited.
As for the conventional technique of the method using the A/D converter and the CPU, the expansion of the adjustment range and the increase in accuracy can be relatively easily realized. When general A/D converter and CPU are used, however, there is an overlapped function part (overhang). Consequently, an unused part in the circuit is large, the circuit scale is increased due to the unused part, and the suppression of increase in the circuit scale is therefore limited.